Axelera AI unveils Titania, an AI inference chip for data centers
Axelera AI has announced its Titania chiplet architecture, utilizing LPDDR6 instead of HBM to target AI inference in existing data centers at lower power consumption.
- Titania is Axelera AI's third-generation silicon architecture, featuring a chiplet design and programmable RISC-V cores.
- The company claims up to 7x higher performance per watt and up to 20x better TCO compared to today's best data center servers.
- Each package supports 128 GB of LPDDR6 memory, eliminating reliance on scarce HBM.
- Titania is slated for production in Q3 2027, with the company securing over $300 million in order commitments.
Table of Contents
Titania targets large-scale AI inference
Axelera AI has unveiled details about Titania, its third-generation silicon architecture designed around chiplets. The goal is to deliver high-performance AI inference within the power and thermal envelopes of existing data centers. Today's highest-density GPU systems typically require liquid-cooled racks exceeding 100 kW.
Each system-in-package (SiP) houses two Titania chiplets. The package will be available in multiple form factors, from standard PCIe cards to OCP-compliant UBB boards with eight OAM modules connected in a scale-up network. OEM partners will distribute air- or liquid-cooled inference servers. According to the company, Titania has already secured over $300 million in pre-order commitments.
The company claims targets of up to 7x higher performance per watt and up to 20x better TCO. These figures are vendor-provided and have yet to be independently verified.
D-IMC architecture and LPDDR6 memory
Titania builds upon the Digital In-Memory Computing (D-IMC) architecture from Metis and Europa. The new generation adds floating-point support, more small cores, and improved data dispatching. Software runs on the Voyager SDK, featuring native support for tensor, expert, and pipeline parallelism, as well as speculative decoding and KV cache offloading.
Instead of HBM, Titania utilizes lower-cost, readily available LPDDR6, delivering 128 GB per package at lower power draw. The company argues that for sparse mixture-of-experts models, memory capacity and utilization matter more than peak bandwidth. This approach also sidesteps HBM supply constraints and complex packaging requirements.
AX8 reference server and roadmap
The AX8 reference server utilizes eight SiPs housed in an air-cooled 4U chassis. This configuration delivers 20 PFLOPS at FP8, 1 TB of memory, and 19.6 TB/s of bandwidth, with typical power consumption of 5 - 6 kW. A single server can accommodate a 1.6-trillion-parameter model at FP4 with headroom for KV cache. A 15 kW rack can host two servers, while an air-cooled 30 kW rack can support five.
The Titania PCIe card is designed as a drop-in replacement for the Axelera Server 250p, a four-chip Europa FHFL card, allowing existing models to transition without re-porting. The chip also features 8K decoding and 4K encoding with H.265 and AV1, offloading video processing from host CPUs. Titania is scheduled to enter production in Q3 2027, with deployment commitments extending into early 2028.
Designed in Europe
Titania is being developed in Europe with support from the DARE initiative under the EuroHPC Joint Undertaking. Axelera AI will present technical details at SC26 from November 15 to 19 in Chicago, at booth 3251 in McCormick Place.
Opting for LPDDR6 instead of HBM is a noteworthy direction, as HBM supply bottlenecks remain a headache for many AI chipmakers. However, the claimed 7x and 20x improvements are vendor targets, and the product will not enter production until 2027. Readers should wait for independent benchmarks, particularly concerning real-world bandwidth when running massive models, before drawing comparisons to current GPUs.
Source: TechPowerUp
Reviewed by: Hero Association
